The invention relates to many kinds of integrated circuit devices, for example application specific gate array devices, PLAs, microprocessors, and custom integrated circuit devices. However, the invention will be described in connection with field programmable integrated circuit devices (FPGAs). Therefore FPGAs are described in some detail here. FPGAs such as those made by Xilinx, Inc. comprise programmable elements and interconnect devices which are programmed by turning on selected transistors. FIG. 1 shows the architecture of a prior art FPGA integrated circuit device made by Xilinx, Inc. Around the perimeter of the chip are input/output buffers (IOBs) such as IOB1 through IOB8. In the interior of the chip are configurable logic blocks (CLBs) such as CLB1 through CLB4. Also in the interior of the chip are switch boxes such as SB1 through SB4. For simplicity, only a few IOBs, CLBs and switch boxes are labeled. Not shown in FIG. 1 is a structure of interconnect lines which run horizontally and vertically from one switch box to another. Also not shown are input and output lines which extend outward from the CLBs in all four directions. However, dots in FIG. 1 represent programmable connections from the interconnect lines in the interconnect structure to lines extending from the CLBs. The switch boxes include a plurality of programmable transistors which can connect one line entering the switch box to other lines entering the switch box. A data book entitled "The Programmable Gate Array Data Book", .COPYRGT.1992 available from Xilinx, Inc. at 2100 Logic Drive, San Jose, Calif. 95124 describes these IOBs, CLBs and switch boxes in more detail. Such devices are also described in Freeman U.S. Pat. No. 4,870,302, incorporated herein by reference.
Functions performed by the CLBs are selectable, and the interconnections between IOBs and CLBs are selectable. Certain of the IOBs have special functions, and during configuration are used for loading the bit stream for configuring the remainder of the chip. After configuration is complete these IOBs used for configuration act as other IOBs. Most external pins are connected to pads which connect to IOBs. However, certain external pins are dedicated to power, ground, and clock lines.
When a Xilinx FPGA device is not powered up, it is not programmed to have any particular configuration. Configuration information is loaded into the chip after the chip is powered up. To select a desired configuration, a user (with the aid of sophisticated software) selects a set of transistors to be turned on and another set to be turned off to achieve the desired configuration. The software generates a bit stream to select the transistors to be turned on or off for the desired configuration. The bit stream is loaded into the FPGA through a shift register such that each bit is eventually loaded into the memory cell for which it was intended. Then the information in the collection of memory cells turns on or off specific transistors to implement the desired configuration. A transistor is programmed by loading a value into a memory cell which drives the gate of the transistor. A memory cell may control more than one transistor. Xilinx uses a lookup table to represent a logic function and a set of memory cells actually represents the logic function.
IOBs may be configured as off, input, output, or input/output ports. FIG. 2 shows in more detail an IOB such as IOB1 of FIG. 1. The IOB includes an output buffer 21 and an input buffer 22. These buffers are CMOS circuits. Both are connected to I/O pad 23 which is directly connected to an external pin of the integrated circuit. If I/O pad 23 were left floating during configuration, it could move to an intermediate voltage level. It is well known that CMOS input voltages should not remain at intermediate voltage levels because P-channel and N-channel transistors in series between power and ground might be turned on simultaneously, drawing undesirably large currents. In the IOB of FIG. 2, I/O pad 23 should not be left floating because a floating input to buffer 22 can produce an undesirable current. To prevent this, Xilinx provides a weak pullup transistor 27 which is resistive in its on state, as represented by resistor 26. During configuration, transistor 27 is turned on by pullup control logic circuit 28 (typically a global signal for all IOBs) When configuration is complete, pullup transistor 27 is turned off. I/O pad 23 (a large capacitance element) then moves to a voltage determined by the configuration state. If I/O pad 23 is not to be used, the user loads a logical 1 into memory cell 38 or 39 to turn on pullup transistor 41 or pulldown transistor 42. At the end of configuration, the high DONE signal turns on transistor 45. The resulting constant Vcc or ground signal on pad 23 can be used to cause input buffer 22 to provide a power or ground signal in addition to preventing the input of buffer 22 from floating.
Also shown in FIG. 2 is slew rate control means 29, which selects between a state in which output buffer 21 provides fast slew response to a signal on line 36, and a state in which output buffer 36 provides slow slew response to the signal on line 36.
Ground Instability
A problem may occur at the point where configuration is complete and many output buffers 21 are simultaneously leaving their high impedance states. If many output buffers 21 are to provide a logical low voltage level, and many pads 23 must simultaneously switch from the high logic level during configuration to a logic zero level to begin operation, the temporary current flow from the load at the pad to the ground line and other structures which are switching to logic zero may pull the ground line voltage level high enough to disturb input logic signals of the chip and cause logic malfunction of the chip or other chips in a system which may be connected to this chip.
Similarly, during testing for current leakage, the output buffers 21 will be held in their high impedance state. After testing, a large number of IOBs may transition from a high state to a low state simultaneously. When lines 34 in many IOBs simultaneously take output buffers 21 out of their high impedance states, low values stored in flip flops 31 or on output lines 35 will be applied to I/O pads 23, causing a current flow from pads 23 through buffers 21 to the ground line, again undesirably pulling up the ground line.
It is desirable to minimize such fluctuation in ground voltage.